Delay elements vary with process, voltage and temperature variations. Previous solutions for generating delays require that delays be tested to ensure the desired specification parameters have been met. An example of such a conventional delay generation is shown in the circuit 10 of FIG. 1. The circuit 10 generally comprises a divide block 12 and a delay line 14. The divide block 12 has an input 15 that may receive a periodic frequency from a voltage control oscillator (VCO), not shown. The divide block 12 has a first output 16 and a second output 18. The output 16 generates a clock signal CLK1 that may be an integer divided clock of the signal receive at the input 15. The output 18 presents a signal CLK2 that may be an integer divided clock of the signal received at the input 15. The delay line 14 delays the signal presented at the output 18 to present a signal CLK2. The signal CLK2 is delayed from the signal CLK1 by an amount defined by the delay line 14. The circuit 10 suffers from a variety of problems including variations caused by process, voltage and temperature variations. Additionally, the circuit 10 is difficult to model, may be sensitive to load variations and may introduce jitter. The introduction of jitter is often the result of slow-edge transitions and delay modulation within delay line 14 (i.e., the delay is a function of the voltage (f(V)).
Referring to FIG. 2, a circuit 20 illustrates a simplified view of a second conventional approach for delay generation. A circuit 20 comprises a number of delay elements 22a-22n. A number of outputs (i.e., phase1, phase2 and phaseN) represent internal taps from a VCO. By tapping the VCO ring elements, the overall VCO layout may be complicated, which may be particularly true in a design application where the internal design of the VCO is not convenient to alter. Additionally, by tapping the ring elements of the VCO, each element has an additional load, which may affect the ultimate maximum frequency of oscillation of the VCO. Additionally, it may be difficult to implement synchronous divides from different clock phases of a VCO.